The present invention relates to a semiconductor device having a nanostructure and a method of manufacturing the same.
A structure having a semiconductor nanocrystal formed in the nanometer order can be applied to various types of devices. Many reports have been made on the nanostructure including a manufacturing method thereof. However, most of the techniques thus reported are so specific that they cannot be adapted to conventional semiconductor mass-production processes.
To explain more specifically, nanocrystals are first formed in a gaseous phase by a low pressure CVD or a plasma CVD and then deposited on a substrate which has been cooled at a low temperature in the conventional method. However, the conventional method has a drawback in that particles are generated in a nanoscale device mass production process. Therefore, this method has a poor adaptability to conventionally employed semiconductor processes. In addition, nanocrystals formed in a gaseous phase tend to make a complex on the substrate surface, it is therefore difficult to distribute desired nanocrystals uniformly.
On the other hand, in a conventional large scale integration circuit, a semiconductor device called MOS has been used. Integration level of the MOS has been increased year by year. In 1996, the gate length of a 265-bit DRAM was 0.25 .mu.m; however, it is estimated that the gate length will be 0.18 .mu.m in a 1 G-bit DRAM in 2000 and 0.13 .mu.m in a 4 G bit DRAM in 2005. In this manner, the miniaturization of the DRAM is accelerated.
Whereas, a currently-used miniaturization technique using photolithography has a limit in reducing the size. Numerous problems exist in a so-called post-photographic technology such as electron beam (EB) exposure and an X-ray lithography.
When light exposure is made by the EB device emitting an electron beam with a radius of 10 nm-order, the resultant processing limit is at least 50 nm due to a resolution limit intrinsic to a resist material.
When the minimization processing is made by X-rays, a synchrotron radiation method is usually employed. The synchroton radiation method requires an immense investment in plant and equipment. Nonetheless, a production efficiency can not be improved in proportion to the immense investment. Hence, it is considered unrealistic to put the X-ray minimization technique in practical use. In addition, the X-rays are harmful to human health due to radiation.
For the reasons mentioned above, it is considered so far difficult to attain the mass production of a semiconductor device having a gate length of 0.05 .mu.m (50 nm) or less.
On the other hand, a nanoscale device called a single-electron device has been studied with the view toward miniaturizing the device. The nanoscale device has a sufficiently small capacitance C. When charging energy (e.sup.2 /(2C)) stored in a tunnel junction is sufficiently larger than temperature fluctuation (almost equal to KT), that is, (e.sup.2 /(2C)&gt;kT), tunneling of electrons is suppressed. This phenomenon is caused by so-called "coulomb blockade". The coulomb blockade provides a threshold in current-voltage characteristics. Because of the presence of a threshold as well as a low power consumption, many application ideas for the single-electron device have been proposed including a three terminal transistor and a memory.
To exercise the coulomb blockade effect and to operate the single-electron device at a room temperature as a general device, it is necessary to form a small tunnel junction having about aF (10.sup.-18 farad) in terms of a capacitance value.
It has been confirmed that the coulomb blockade effect exercises at a room temperature by using a specific method shown in the papers of IEDM'93-541 (Yano et al), IEDM'94-938 (Takahashi et al.) and the like. However, it is very difficult to manufacture such a small tunnel junction by the currently-used general semiconductor manufacturing technology.
Since the coulomb blockade effect is confirmed to be obtained at a room temperature in practice, the coulomb blockade is expected as a novel technique capable of being incorporated in an LSI circuit. However, the conventional single-electron device and a manufacturing method thereof have the following problems, so that it has not yet been actually applied to an LSI device.
(1) A generally employed LSI manufacturing process including a lithographic method employing a photomask has a limit in miniaturization. Therefore, it is difficult to manufacture such a small capacitance sufficient to observe the coulomb blockade at a high temperature.
(2) In the coulomb blockade, the tunnel barrier defining essential tunneling characteristics has hitherto been significantly limited by the manufacturing method. Therefore, it is difficult to manufacture single-electron devices each having different characteristics depending upon applied circuits.
(3) The tunnel junction through which electrons tunnel in the general single-electron device is formed by using an insulating material such as an oxide film or a material having a high energy barrier in a band diagram. Since the energy barrier is high for electrons, a tunneling probability of an electron itself will exponentially decrease if the thickness of the energy barrier is not reduced. It is therefore necessary to control the thickness of the oxide film very precisely. This makes it more difficult to manufacture a uniform device.